Research on fault injection system of FPGA in irradiation environment

Overview: SRAM FPGAs have attracted increasing attentions in aerospace applications due to their low cost, rich logic resources, and reconfigurability. However, SRAM cells are highly susceptible to the effects of radiations, manifested as single event upsets (SEU), thus hindering the applicability of FPGA in the aerospace field. The configuration RAM (CRAM) is the largest number of memory cells in FPGA chip. Considering the direct impact of CRAM on the user circuit logic, the research object of this paper is CRAM. In order to test the failure rate of CRAM in radiation environment, the FPGA needs to be irradiated under the accelerator beam, which can simulate the space environment more realistically. However, it is expensive and the test period is long. Therefore, the artificially designed fault injection system to simulate the SEU can quickly and inexpensively test the reliability of the design on the FPGA. Injecting fault into CRAM can be achieved through the external interface (JTAG or SelectMAP) or the internal interface (internal configuration access port, ICAP). For internal fault injection, most designs use on-board processors. Starting from Virtex-6/Spartan-6, Xilinx provides a PicoPlaze-based SEM (soft error mitigation) IP core, which can implement fault injection, fault repair, fault classification, and other functions. Since the PicoPlaze processor does not have an official C compiler and the instruction space is extremely small (1024 words), the SEM controller cannot be flexibly reprogrammed to design a different fault repair mechanism. The Virtex-5 series FPGAs studied in this paper do not have a dedicated SEM IP core which is officially provided, so a self-designed fault injection system is required. This article studied the frame structure of Xilinx FPGA CRAM, giving the method of extracting the frame structure and providing the order of frames in the bit stream file. The structure of the intermediate file of SEM IP core is also analyzed to get the positions of essential bits. Performing 0/1 flipping on the essential bits is a way to simulate the SEU problem. A PC-side interface is designed to implement a human-machine interaction. The fault injection system is implemented on FPGA chip, and the read and write of the CRAM data are realized through ICAP without the need of the processor. The fault injection system is placed on resources that are not used by the circuit under test, occupying about one percent of the FPGA resources, which greatly saves resource overhead. The operation of flipping and repairing test classifies essential bits into the following categories: the non-critical and repairable, the non-critical and unrepairable, the critical and repairable, the critical and unrepairable, and the residual bits that affect other non-masked bits in the same frame. The classification results can be used to protect key bits in subsequent fault repairing. In addition, a fault injection test on the triple modular redundancy (TMR) circuit is performed to verify the effectiveness of TMR for SEU protection. For TMR circuit, the proportion of its key bits will be greatly reduced but not to zero, which indicates that the TMR can reduce failure rate caused by SEU but cannot completely avoid this fault. Since TMR cannot eliminate the accumulation of SEU faults, it is necessary to supplement other fault-tolerant measures such as internal scrubbing and external scrubbing in practical engineering applications.