光电工程  2019, Vol. 46 Issue (7): 190194      DOI: 10.12086/oee.2019.190194

1. 中国科学院微电子研究所，北京 100029;
2. 中国科学院大学，北京 100049

A high-performance CMOS FDMA for pulsed TOF imaging LADAR system
Jiang Yan1,2, Liu Ruqing1, Zhu Jingguo1, Wang Yu1
1. Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;
2. University of Chinese Academy of Sciences, Beijing 100049, China
Abstract: This paper presents a high bandwidth and low noise fully differential main amplifier (FDMA) for pulsed time-of-flight (TOF) imaging laser detection and ranging application (LADAR), which serves to amplify the small pulse echo signal. The cascaded architecture and active inductor technology are used to enlarge the bandwidth of the circuit and reduce the chip area. The cascaded gain stages, which adopted DC offset isolation circuit, are more robust to the alteration of process. A large bandwidth amplifier (LBA) and an output buffer (OB) structure have been designed to enhance the drive capabilities. Besides, in order to adapt the demand of the LADAR system, the amplifier receiver's bandwidth has been limited by using an inter-stage bandpass filter. Implemented in CSMC CMOS technology, the FDMA chip realizes the -3 dB bandwidth of 730.6 MHz, and an open loop gain of 23.5 dB with the bandpass filter worked. The input-referred noise voltage is 2.7 nV/sqrt(Hz), which effectively reduces the system noise. This chip that occupies 0.25 mmc×0.25 mm in area consumes a power dissipation of 102.3 mW from the 3.3 V power supply. As a part of the integrated chip of the laser radar system, it can better meet the requirements of system.

1 Introduction

As an optical remote sensing technology, the laser detection and ranging (LADAR) system has been used in many fields[1-3], including the auxiliary driving, intelligent robot for target identification, and the 3D imaging. The pulsed time-of-flight (TOF) LADAR system that measures the distances to targets by emitting and detecting laser echoes accurately has the unique advantage of long detection range compared to other measurement methods such as the continuous-wave optical phase method[4-5].

A block diagram of a typical TOF LADAR system is shown in Fig. 1. As shown in the figure, the LADAR system is composed of a pulsed laser transmitter, an amplifier receiver, a time-to-digital converter (TDC), an analog-digital converter (ADC), and a micro-processor. The pulsed laser transmitter generates a start signal and simultaneously emits an optical pulse signal. After focused by some optical components, the laser pulse signal launches towards the target, and an echo signal will be produced and reflected back when the optical pulse encounters the target. The amplifier receiver, on which this paper focuses, amplify the reflection signal from the target by receiver’s optical component to the analog-digital converter, and generates the arrival timing signal (stop) of the echo signal to the time-to-digital converter[6]. In the signal processor, according to the flight time, the distance between the target and the receiver can be calculated through the LADAR formulas by using the micro-processor.

 图 1 Block diagram of a typical TOF LADAR

The amplifier receiver which mainly includes a photoelectric detector and analog front-end circuits converts the optical pulse echo signal into an electrical pulse. The photoelectric detector usually employs an avalanche photodiode (APD) because of the high sensitivity. The analog front-end circuits, which mainly consist a trans-impedance amplifier (TIA) and a main amplifier, are used to convert a current signal to a voltage signal for the analog-digital converter and time-to-digital converter to discriminate. However, only by using TIA it cannot satisfy the demand for the remote detection applications. Since the transmit power of the pulse laser are limited, in active imaging system, the performance of the main amplifier becomes a critical issue. Therefore, a high-performance main amplifier is a key component to the LADAR system.

In this paper, a fully differential main amplifier chip has been implemented in a CSMC CMOS process. The proposed amplifier applied active inductor, which is used to reduce the chip area and enlarge the bandwidth of the circuit. In order to apply for LADAR system, this work achieves an inter-stage bandpass filter by reusing the DC offset isolation circuit. Section 2 describes the LADAR system and proposed amplifier receiver. Section 3 introduces the details of fully differential main amplifier. The measurement results of the chip are shown in Section 4, and Section 5 summarizes the design.

The amplifier receiver is mainly to amplify the moment of the weak optical echo signal which is come from the target. The input current signal of the photoelectric detector produced can be acquired by the well-known radar principle and responsibility of APD.

 ${i_{{\rm{opt}}}}(R) = {R_{{\rm{APD}}}}\frac{{{P_{\rm{T}}}{\tau _{\rm{T}}}\rho {A_{\rm{R}}}}}{{{\rm{ \mathsf{ π} }}R_{\rm{S}}^2}}\;,$ (1)

where ${R_{{\rm{APD}}}}$ is the responsibility of APD, pT is the peak power of the laser transmitted pulse, ${τ_{\rm{T}}}$ is the transmission of the optical system, $\rho$ means the reflection coefficient of the target, ${A_{\rm{R}}}$ is the active area of the receiver lens. Last, and ${R_{\rm{S}}}$ is the distance between the target and receiver.

Usually, an avalanche PD (APD) is used as the photodetector because of the high responsivity. The gain of a Si APD can be 50 A/W, but the InGaAs APD has the typical gain of only 10 A/W. Therefore, the minimum detectable echo signal for the receiver will be only few tens of nW by using InGaAs APD.

The signal-to-noise ratio (SNR) can be calculated by the radar formula[7]. In order to suitable the practical applications, the requirement of the SNR is over 5 in the general hundreds of meter detection LADAR system. Further, the SNR over 10 would be advantageous for mm-level accuracy.

Figure 2 shows the block diagram of the proposed amplifier receiver. In Fig. 2, the proposed amplifier receiver consists of two parts: trans impedance amplifier (TIA) and main amplifier. The TIA is an analog circuit that converts the input current pulse signal from the APD into voltage. And the main amplifier’s task is to further amplify the small voltage signal to an appropriate level so that the voltage can be process by the followed circuit such as the TDC and ADC. However, only by using TIA it cannot satisfy the demand of the voltage for the remote detection system. Therefore, the performance of the main amplifier influences the optical pulse receiver largely.

 图 2 Block diagram of the proposed amplifier receiver

The main amplifier circuit should have enough wide bandwidth to keep the pulse waveform linearly magnified. However, excessive bandwidth would lead to additional noise entering the receiver, due to the signal-to-noise ratio (SNR) of the receiver deteriorated. The bandwidth (BW) as a critical limit can be approximately expressed as follows[8]:

 $BW \ge \frac{{0.35}}{{{t_{\rm{r}}}}}\;{\rm{or}}\;\frac{{0.44}}{{{t_{\rm{r}}}}},$ (2)

where tr is the rise edge of the time signal. For general applications, the pulsed laser with a peak power of 20 W ~75 W and a width of 3 ns~20 ns is needed[9]. This means that a narrower pulsed echo requires about 100 MHz ~200 MHz BW of the whole receiver channel. In the design, BW of the fully differential main amplifier (FDMA) is demanded over the 500 MHz. At the same time, in order to meet the LADAR system application, this work designs an inter-stage bandpass filter by reusing the DC offset isolation circuit to limit system noise.

3 Circuit description

 图 3 The architecture of fully differential main amplifier

In conventional integrated amplifier systems, the cascaded gain stage (CGS) is widely used to achieve optimum results for both high gain and wide bandwidth. Assuming that the circuit consists of n identical gain stages with one pole frequency response, for the multilevel cascaded gain stages, the total bandwidth can be calculated as following (3):

 $B{W_{{\rm{tol}}}} = B{W_{\rm{s}}} \times {({2^{\frac{1}{n}}} - 1)^{\frac{1}{2}}},$ (3)

where BWs is the bandwidth of each gain stage, and BWtol is the whole bandwidth of CGS. Therefore, the gain bandwidth product of each gain stage given by (4):

 $GB{W_{\rm{s}}} = \frac{{B{W_{{\rm{tol}}}}}}{{{{({2^{\frac{1}{n}}} - 1)}^{\frac{1}{2}}}}} \times A_{{\rm{tol}}}^{\frac{1}{n}},$ (4)

where Atol is the total gain of CGS, and GBWs is the gain bandwidth product of each gain stage.

According to above formulas, there are shown that the increasing number of the gain stages can directly achieve higher gain. Consequently, the simplest way to enlarge the cascaded gain bandwidth product is to make the number of stages as larger as possible. However, this approach will not only result in a significant increase in the power consumption and area, but also make a rapid accumulation of noise from the gain stage, which has a significant impact on the amplifier circuit stability. In the practical design, the maximum number of stages is usually limited to below five[11].

In the designed pulsed TOF imaging LADAR system, the proposed FDMA needs to meet the requirements as following: ${G_{{\rm{tol}}}} = 20\log ({A_{{\rm{tol}}}}) \ge 20\; dB$, $B{W_{{\rm{tol}}}} \ge 600\; {\rm{MHz}}$. For n=4, it can be calculated that the BWs should exceed 1.4 GHz and each stage should have a gain of approximately 5.25 dB. Therefore, considering the gain bandwidth and noise figure, the CGS which contains four the same gain stages is designed in the paper.

3.1 Active inductor

The element structure of the main amplifier is the fully differential cascaded stage. However, it is hard to achieve such a wide bandwidth based on CMSC 0.5 μm CMOS process. The active inductor technique is adopted to alleviate the bandwidth degradation, because the spiral inductor with a high inductance will occupy a lot of area and it is difficult to implement in CMOS process[12]. Fig. 4 shows the structure of the proposed CGS with an active inductor load.

 图 4 The amplifier structure with active inductor technique

The simplified small-signal analysis model of the active inductor load, which consists of a MOS transistor M4 and a resistor Rg, is shown in Fig. 5. Usually, there are ${C_{{\rm{gs4}}}} \ge {C_{{\rm{gd4}}}}$, ${C_{{\rm{gs4}}}} \ge {C_{{\rm{ds4}}}}$ and ${g_{{\rm{m4}}}} \ge {g_{{\rm{ds4}}}}$, so that the Cgd4, Cds4, gds4 can be neglected.

 图 5 Small-signal model of an active inductor

The equivalent impedance of the active inductor can be given as following[13]:

 ${Z_{{\rm{in}}}} = \frac{{1 + {R_{\rm{g}}}s{C_{{\rm{gs}}4}}}}{{{g_{{\rm{m}}4}} + s{C_{{\rm{gs}}4}}}},$ (5)

where Zin is the output impedance. Cgs4 is the gate-source capacitance of MOS transistor, and gm4 is the trans-conductance of MOS transistor. Therefore, the equivalent inductance L and resistance R can be calculated as following[14]:

 $L = \frac{{\frac{{{R_{\rm{g}}}}}{{{\omega _{\rm{T}}}}} + \frac{1}{{{g_{{\rm{m}}4}}{\omega _{\rm{T}}}}}}}{{1 + {{(\frac{\omega }{{{\omega _{\rm{T}}}}})}^2}}}\;R = \frac{{{R_{\rm{g}}}{{(\frac{\omega }{{{\omega _{\rm{T}}}}})}^2} + \frac{1}{{{g_{{\rm{m}}4}}}}}}{{1 + {{(\frac{\omega }{{{\omega _{\rm{T}}}}})}^2}}}.$ (6)

The ωT is the unity current gain angular frequency. In order to avoid undesirable peaking on the frequency response, the resistance Rg should be designed carefully according to the capacitive load of the following stage. The active inductors perform an impedance of Rg at low frequency. When the frequency is sufficiently high, the inductor L is formed by Rg and Cgs4 so that the impedance of the gain stage is increased. The impedance change is similar to the inductor and the frequency within a certain range[15]. The gain of the common source amplifier that has a structure of the active inductor load can be expressed as following (7):

 ${A_{\rm{V}}} = \frac{{{g_{{\rm{m}}2}}}}{{{g_{{\rm{m}}4}}}} = \sqrt {\frac{{{W_2}/{L_2}}}{{{W_4}/{L_4}}}} .$ (7)

The formula reveals that the stage’s gain only has received the influences on the dimension of the input and load transistors. Consequently, the circuit that uses the active inductor structure has stronger capacity against to the alteration of temperature and process. Besides, the formula can be obtained as (8):

 $\frac{{{V_{{\rm{out}}}}}}{{{V_{{\rm{in}}}}}}(s) = \frac{{{g_{{\rm{m}}2}}(1 + s{R_{\rm{g}}}{C_{{\rm{gs}}4}})}}{{{g_{{\rm{m}}2}} + s{C_{\rm{L}}} + {s^2}{C_{\rm{L}}}{R_{\rm{g}}}{C_{{\rm{gs}}4}}}}.$ (8)

Through choosing the appropriate value of the L and R, the bandwidth can be extended largely while maintaining a suppressed gain peak over the frequency range. In summary, based on the above formula, the CGS that consists of four identical gain stages and active inductive load is the optimized choice for this design.

3.2 Inter-stage bandpass filter

During chip fabrication, many non-ideal elements such as the asymmetry layout design and slight deviations in MOS transistor will result in DC offset, especially for cascaded differential gain structure. Since the amplifier that uses the multi-stage cascade structure as a high gain, the DC offset voltage which generated by the preamplifier unit is amplified, resulting in a large shift of the operating point of the post amplifier[16]. Even if the input deviation is small, the amplification of the stages may cause the output buffer to reach the saturation.

In order to stabilize the operating point and DC gain, the structure of offset voltage compensation loop is required. This circuit employs capacitive coupling to eliminate DC offset. As shown in Fig. 6, C1 and C2 are DC blocking capacitors for eliminating DC offset. Ma1~Ma8 (Mb1~Mb8) are NMOS transistors with the same substrate and source terminals to provide a self-bias voltage for the amplifier.

 图 6 The inter-stage bandpass filter of the schematic

Excessive bandwidth can cause additional noise to enter the receiver, which degrades the receiver's signal-to-noise ratio (SNR). Therefore, the bandwidth of the whole amplifier chains should be limited to a certain range. In order to meet the needs of the LADAR system, this work achieves an inter-stage bandpass filter by reusing the DC offset isolation circuit to mitigate the problem that the coupled capacitances occupy a lot of area in the CMOS process and lead to attenuate the signal. The simplified equivalent formula can be calculated as (9):

 ${f_{\rm{L}}} = \frac{1}{{2{\rm{\pi }}{R_{\rm{g}}}{C_{\rm{s}}}}}$ (9)

where ${f_{\rm{L}}}$ is the bandwidth of bandpass filter, ${R_{\rm{g}}}$ is the equivalent resistance of the NMOS transistors and ${C_{\rm{s}}}$ is C1 and the parasitic capacitors of the NMOS transistors.

3.3 Output stage circuit

The output stage circuit is used to enhance the drive capability of the FDMA circuit, which includes two parts of modules. The large bandwidth amplifier (LBA) stage was employed before the output buffer (OB) to solve the problem that the parasitic capacitance causing by the large input transistors of OB results a reduction in bandwidth[17-18]. The architecture of the CGS circuit was adopted in the large bandwidth amplifier. It works as the former driver stage to eliminate the side effect of the output buffer. At last, the output buffer (OB) was designed to drive the PCB transmission lines and the load capacitance of the followed external circuit. As shown in Fig. 7, based on actual experience, the load resistors of the output buffer (OB) should be designed according to the actual situation and specific package.

 图 7 The large bandwidth amplifier (a) and output buffer schematic (b)
4 Measure results

The proposed FDMA is fabricated in a CSMC 0.5 μm 2P3M Mixed CMOS technology. Fig. 8 shows the photograph of the fully differential main amplifier chip with an active area of 0.25 mmc×0.25 mm, a core area of 0.16 mmc×0.16 mm, and several extra pads were added for measurement. This chip consumes a power dissipation of 102.3 mW from 3.3 V voltage supply, in which the output buffer (OB) circuit consumes 73.2 mW. As shown in Fig. 9, the proposed chip was packaged in QFN40 and mounted on the test printed circuit board (PCB) and Fig. 10 displays the test apparatus and the environment.

 图 8 Photograph of the fully differential main amplifier chip

 图 9 PCB test board

 图 10 Test apparatus and environment

The open loop gain and bandwidth of the proposed chip were measured by the Agilent vector network analyzer (E5071C)(Fig. 11).

 图 11 Measured S parameters with the inter-stage bandpass filter

From Fig. 11, it can be seen that the open loop gain of the chip is about 23.5 dB at 100 MHz, the -3 dB bandwidth is 730.6 MHz. The -3 dB bandwidth is limited to a certain range, in order to adapt the demand of the LADAR system.

Figure 12 shows the measured noise spectrum from the Agilent spectrum analyzer (N9020MAX). The input-referred noise voltage of the amplifier is 2.7 nV/sqrt(Hz) at 100 MHz with the 50 Ω input.

 图 12 Measured noise spectrum of the output

As shown in the Fig. 13, the measured response of the FDMA with the power 1 μW and 3 ns pulse width input in the system from the Tektronix Oscilloscope 5104B. The Fig. 14 illustrates the measured frequency response of the FDMA with the laser pulse frequency 10 kHz.

 图 13 Measured amplitude response of the FDMA

 图 14 Measured frequency response of the FDMA
5 Conclusion

An integrated a fully differential main amplifier for pulsed TOF imaging LADAR system with high bandwidth and low noise has been proposed and fabricated in CSMC 0.5 μm CMOS technology. The FDMA includes proposed cascaded gain stages, which enhance wide bandwidth performance, a large bandwidth amplifier (LBA) and an output buffer (OB) and the bandpass filter. The four levels cascaded architecture and active inductor technology are used to overcome the inadequate bandwidth problem and reduce the chip area under conventional process. By using the inter-stage bandpass filter, the -3 dB bandwidth is limited to improve the SNR, in order to meet the demand of the LADAR system. The measurement results have confirmed that the proposed FDMA chip achieves the -3 dB bandwidth of 730.6 MHz, and an open loop gain of 23.5 dB with the bandpass filter worked. The input-referred noise voltage is 2.7 nV/sqrt(Hz), which effectively reduces the system noise. This chip that occupies 0.25 mmc×0.25 mm area consumes a power dissipation of 102.3 mW from the 3.3 V power supply. As a part of the integrated chip of the laser radar system, it can better meet the requirements of system.