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Design and simulation of the on-chip integrated CdTe waveguide. (a) The 3D structure diagram of the CdTe/CdS/Si waveguide. The width (WCdTe), height (
Waveguide fabrication flow chart and scanning electron microscope images. (a) The waveguide fabrication flow chart; (b) The waveguide surface topography. The height and width of the waveguide are 8.5 µm and 22 µm, respectively. The angle between the side wall of the waveguide and the CdS layer is 90°; (c) The side and top topography of the waveguide
(a) The experimental setup diagram. The inset shows the field distribution of the TE mode at 1030 nm wavelength in the waveguide; (b) The broadened spectrum from the waveguide at different pump power
Spectral broadening caused by self-phase modulation (SPM) in the CdTe waveguide based on GNLSE. (a) The output spectrum of the waveguide at different peak power (5 kW~20 kW) pumped at 1030 nm wavelength; (b), (d), (f), (h) The time-domain evolution diagrams of SCG process; (c), (e), (g), (i) The frequency-domain evolution diagrams of the SCG process