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All-optical computing based on convolutional neural networks
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Abstract
The rapid development of information technology has fueled an ever-increasing demand for ultrafast and ultralow-energy-consumption computing. Existing computing instruments are pre-dominantly electronic processors, which use electrons as information carriers and possess von Neumann architecture featured by physical separation of storage and processing. The scaling of computing speed is limited not only by data transfer between memory and processing units, but also by RC delay associated with integrated circuits. Moreover, excessive heating due to Ohmic losses is becoming a severe bottleneck for both speed and power consumption scaling. Using photons as information carriers is a promising alternative. Owing to the weak third-order optical nonlinearity of conventional materials, building integrated photonic computing chips under traditional von Neumann architecture has been a challenge. Here, we report a new all-optical computing framework to realize ultrafast and ultralow-energy-consumption all-optical computing based on convolutional neural networks. The device is constructed from cascaded silicon Y-shaped waveguides with side-coupled silicon waveguide segments which we termed “weight modulators” to enable complete phase and amplitude control in each waveguide branch. The generic device concept can be used for equation solving, multifunctional logic operations as well as many other mathematical operations. Multiple computing functions including transcendental equation solvers, multifarious logic gate operators, and half-adders were experimentally demonstrated to validate the all-optical computing performances. The time-of-flight of light through the network structure corresponds to an ultrafast computing time of the order of several picoseconds with an ultralow energy consumption of dozens of femtojoules per bit. Our approach can be further expanded to fulfill other complex computing tasks based on non-von Neumann architectures and thus paves a new way for on-chip all-optical computing. -
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References
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Supplementary Information for All-optical computing based on convolutional neural networks 
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Figure 1.
General architecture of the all-optical computing framework. (a) The CNN architecture showing the connections between adjacent layers:
${{ \widetilde {\text{X}}}\,^{\text{l}}={ \widetilde {\text{W}}}_{ {l,l}-1}{ \widetilde {\text{X}}}\,^{ \text{l}-1}}$ $ {\widetilde {\text{X}}}\,^{ \text{l}} $ $ { \widetilde {\text{X}}}\,^{ \text{l}-1} $ $ {\widetilde {\text{W}}}_{\text{l,l}-1} $ -
Figure 2.
Weight regulation. (a) SEM image of Y-shaped waveguides side-coupled silicon weight modulators. Two arms of the “Y” structure waveguide correspond to two kinds of weights. By regulating the length a of weight modulator and the gap width b between two waveguides: (b) The magnitude of weight ω can be continuously adjusted from 0.03 to 0.95. (c) The phase of weight ω can be continuously adjusted from 0 to 2π.
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Figure 3.
All-optical transcendental equation solver. (a) Output light intensity distribution in the output waveguides (k = 1.67). The arrows in the figure correspond to the locations of the solutions. The horizontal axis is the number of discrete waveguides, the vertical axis on the left represents the output signal intensity, and the vertical axis on the right gives the deviation between the experimental output signal and the theoretical value. (b) A graphic representation of solution deviation. The horizontal axis labels the individual solutions, and the vertical axis represents three values of the parameter k. The shade of the color indicates the magnitude of the deviation.
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Figure 4.
Multifarious logic gates. (a) Schematic diagram of the multifarious logic gate operator. Ports A, B are the signal inputs, and ports C1, C2, C3, C4, together constitute the control bits, and Y represents the signal output. (b) Top-view SEM image of the multifarious logic gate operator. (c) 0−1 intensity distribution when the optical CNN device acts as three different types of logic gates. (d) Overlay of three logic function responses in the optical CNN structure. The top red line corresponds to the minimum intensity of “1”, and the bottom red line shows the maximum intensity of “0”.
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Figure 5.
Half-adder. (a) Schematic diagram of the half-adder. Ports A, B are the signal inputs, and C and S represent the Carry and the Sum bit, respectively. (b) Top-view SEM image of the half-adder. (c) Intensity distribution of Sum bit and Carry bit corresponding to three different input signals in the half-adder. The blue lines give the average intensity values of the 0 and 1 logic states.
